nLupo :anarchist_flag: :antrans_flag:<p>I really start to like <a href="https://amikejo.xyz/tags/uxn" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>uxn</span></a> and <a href="https://amikejo.xyz/tags/varvara" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>varvara</span></a>. It's such a minimalist architecture and it's also open source and open standard.</p><p>If I have enough time I'll make a "doom's day" computer in <a href="https://amikejo.xyz/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a> and I'll probably buy one of those small <a href="https://amikejo.xyz/tags/fpgas" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>FPGAs</span></a> from <a href="https://amikejo.xyz/tags/olimex" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Olimex</span></a>.</p>
Recent searches
No recent searches
Search options
Only available when logged in.
mastodon.green is one of the many independent Mastodon servers you can use to participate in the fediverse.
Plant trees while you use Mastodon. A server originally for people in the EU, but now open for anyone in the world
Administered by:
Server stats:
1.2Kactive users
mastodon.green: About · Profiles directory · Privacy policy
Mastodon: About · Get the app · Keyboard shortcuts · View source code · v4.3.7
#verilog
0 posts · 0 participants · 0 posts today
Holly A. Gultiano<p>All the equivalent circuit models of neurons written in an <a href="https://synapse.cafe/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a> would be a cool project</p>
Philip Zucker<p>[New Blog Post] Comparing Two Verilog CPU Implementations using EBMC <a href="https://www.philipzucker.com/td4_ebmc/" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://www.</span><span class="">philipzucker.com/td4_ebmc/</span><span class="invisible"></span></a> <a href="https://types.pl/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a> <a href="https://types.pl/tags/formal" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>formal</span></a></p>
Jack Leightcap<p>Hey all! I'm due for an (re-)introduction: I'm Jack, an engineer in the NYC area from a firmware & cybersecurity background, currently working in something like hardware-software co-design.</p><p>Technical work is often with <a href="https://recurse.social/tags/rust" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>rust</span></a> <a href="https://recurse.social/tags/kicad" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>kicad</span></a> <a href="https://recurse.social/tags/python" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>python</span></a> <a href="https://recurse.social/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a> <a href="https://recurse.social/tags/c" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>c</span></a>, and in all-too-rare moments stuff like <a href="https://recurse.social/tags/haskell" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>haskell</span></a> <a href="https://recurse.social/tags/forth" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>forth</span></a> <a href="https://recurse.social/tags/agda" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>agda</span></a> and <a href="https://recurse.social/tags/prolog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>prolog</span></a><br> <br>I've never been much for social media, usually preferring to keep interests local: a better-detailed <a href="https://recurse.social/tags/introduction" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>introduction</span></a> to follow as I figure this out 🙂</p>
Morgan Arnold<p>quick question about <a href="https://mathstodon.xyz/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a>, or maybe more specifically <a href="https://mathstodon.xyz/tags/yosys" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>yosys</span></a>: i've been messing around with an icebreaker fpga recently, and the ice40up5k chip has four banks of 32k x 8 bit spram built in. i wanted to use this ram in a design, but (either yosys or nextpnr, i'm not sure which is responsible for assigning hdl declarations to actual hardware) won't automatically assign things to this spram, so you have to manually work with it by instantiating a module of type `sb_spram256ka`. my question, then, is why yosys doesn't mind me using here a module that i haven't defined. since i've told it that i'm using an ice40 chip, is it just implicitly defining a bunch of modules?</p>
Forth Co-Processor<p>I will be speaking on Saturday Morning, Jan25th, at the SVFIG meetup about an <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>FPGA</span></a> Vector processor. Here is how it does <a href="https://mastodon.social/tags/vector" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>vector</span></a> multiplies. Starts at 9:30 am California time. <a href="https://mastodon.social/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a></p><p><a href="http://forth.org/zoom" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">http://</span><span class="">forth.org/zoom</span><span class="invisible"></span></a></p>
Markus Osterhoff<p><a href="https://troet.cafe/tags/GutenMorgen" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>GutenMorgen</span></a>, Ihr lieben Frühwürmchen!</p><p>Eine Gruppe Wissenschaftlys zeigte gestern Abend schon reges Interesse an meinem zweiten Poster, das heute dran ist. Nun überlege ich also, das nochmal etwas umzubauen: die Erklärung "Was ist denn so ein <a href="https://troet.cafe/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>FPGA</span></a> überhaupt?" kürzen, dafür dann Blockdiagramm, Datenfluss, <a href="https://troet.cafe/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Verilog</span></a>-Quellcode der beiden wesentlichen Algorithmen drauf.</p><p>Hmm …</p><p>Habt 1 durchdesignten Tag!</p>
PipelineC<p>Gifted a new <a href="https://fosstodon.org/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>FPGA</span></a> dev board this season? 🤓 PipelineC aims to make <a href="https://fosstodon.org/tags/hardware" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>hardware</span></a> description easier for <a href="https://fosstodon.org/tags/embedded" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>embedded</span></a> folks.<br>Check out the new getting start page. Happy to help you get going! <a href="https://fosstodon.org/tags/hdl" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>hdl</span></a> <a href="https://fosstodon.org/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a> <a href="https://fosstodon.org/tags/vhdl" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>vhdl</span></a> <a href="https://fosstodon.org/tags/HLS" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>HLS</span></a> <br><a href="https://github.com/JulianKemmerer/PipelineC/wiki/Dev-Board-Setup" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">github.com/JulianKemmerer/Pipe</span><span class="invisible">lineC/wiki/Dev-Board-Setup</span></a></p>
ianto<p>Today's <a href="https://toot.wales/tags/AdventOfCode" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>AdventOfCode</span></a> part1 was again a surprisingly fast success (anonymous variables in <a href="https://toot.wales/tags/perl" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>perl</span></a> ftw) in private leaderboard, but also weirdly easy which is _always_ a red flag for part2. I'll come back to that later, but meanwhile will make a hardware design for the number generator (<a href="https://toot.wales/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a>), and will also have the 10yo learn how to solve it (<a href="https://toot.wales/tags/python" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>python</span></a>). Thanks a lot to <span class="h-card" translate="no"><a href="https://hachyderm.io/@ericwastl" class="u-url mention" rel="nofollow noopener noreferrer" target="_blank">@<span>ericwastl</span></a></span> for not ruining Sunday with a 3d falling grid problem!</p>
Tommy Thorn<p>I was curious about <a href="https://chaos.social/tags/Bluespec" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Bluespec</span></a> but I couldn't find even a "blink LED" example, so I finally wrote my own. This doesn't show any of the strengths of Bluespec, but this does blink LEDs (on the <a href="https://chaos.social/tags/ULX3S" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>ULX3S</span></a> <a href="https://chaos.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>FPGA</span></a> dev kit). The generated <a href="https://chaos.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Verilog</span></a> looks fine.</p><p><a href="https://github.com/tommythorn/bluespec_blink" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">github.com/tommythorn/bluespec</span><span class="invisible">_blink</span></a></p>
Flux<p>Is 2025 the year of <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>FPGA</span></a> on the desktop? 🤔 </p><p>Please suggest interesting FPGA projects and people to inspire us for the year ahead. 🚀</p><p>I'm working on a 2D graphics accelerator in <a href="https://mastodon.social/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a> and <a href="https://mastodon.social/tags/riscv" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>riscv</span></a> assembler.</p>
ianto<p>First steps completed on this years <a href="https://toot.wales/tags/AdventOfCode" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>AdventOfCode</span></a> pure-hardware challenge (no processor, no software) solution: behavioural <a href="https://toot.wales/tags/verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>verilog</span></a> that solves both parts of day 1.<br>Next step is to implement a hardware bubblesort with registers and a counter, then will replace behavioural model by RTL. I'm not likely to actually get it working on an <a href="https://toot.wales/tags/fpga" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>fpga</span></a> ... but I am stupid enough to try.</p>
PipelineC<p>Come on over to the Discord channel if you want to join the conversation about this fun work 🤓 <a href="https://discord.gg/vBUtmBZcxC" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="">discord.gg/vBUtmBZcxC</span><span class="invisible"></span></a> <a href="https://fosstodon.org/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>FPGA</span></a> <a href="https://fosstodon.org/tags/raspberrypi" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>raspberrypi</span></a> <a href="https://fosstodon.org/tags/pico" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>pico</span></a>-ice <a href="https://fosstodon.org/tags/PipelineC" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>PipelineC</span></a> <a href="https://fosstodon.org/tags/HDL" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>HDL</span></a> <a href="https://fosstodon.org/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Verilog</span></a> <a href="https://fosstodon.org/tags/VHDL" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>VHDL</span></a></p>
PipelineC<p>Have been super pleased with the <a href="https://fosstodon.org/tags/ice40" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>ice40</span></a> <a href="https://fosstodon.org/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>FPGA</span></a> and <a href="https://fosstodon.org/tags/raspberrypi" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>raspberrypi</span></a> board that <a href="https://pico-ice.tinyvision.ai/" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="">pico-ice.tinyvision.ai/</span><span class="invisible"></span></a> sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with <a href="https://fosstodon.org/tags/PipelineC" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>PipelineC</span></a> and boards like the pico-ice 🤓 <a href="https://fosstodon.org/tags/HDL" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>HDL</span></a> <a href="https://fosstodon.org/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Verilog</span></a> <a href="https://fosstodon.org/tags/VHDL" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>VHDL</span></a> <a href="https://fosstodon.org/tags/hardware" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>hardware</span></a> <a href="https://fosstodon.org/tags/embedded" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>embedded</span></a></p>
Forth Co-Processor<p>My new <a href="https://mastodon.social/tags/Introduction" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Introduction</span></a><br> <br>I am building tiny real-time <a href="https://mastodon.social/tags/Forth" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Forth</span></a> co-processors for MicroPython, Circuit Python and RISC-V. On FPGA's a stack machine can be 1/2 the size of a 32 bit RISC-V soft core.</p><p><a href="https://mastodon.social/tags/Forth" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Forth</span></a>, <a href="https://mastodon.social/tags/MicroPython" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>MicroPython</span></a> <a href="https://mastodon.social/tags/CircuitPython" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CircuitPython</span></a> <a href="https://mastodon.social/tags/Riscv" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Riscv</span></a> <a href="https://mastodon.social/tags/StackMachine" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>StackMachine</span></a> <a href="https://mastodon.social/tags/FPGA" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>FPGA</span></a> <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Verilog</span></a><br><a href="https://mastodon.social/tags/realtime" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>realtime</span></a></p>
Alfred M. Szmidt<p>Calling all <a href="https://mastodon.social/tags/HDL" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>HDL</span></a> hackers! I need help in putting the <a href="https://mastodon.social/tags/MIT" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>MIT</span></a> <a href="https://mastodon.social/tags/CADR" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>CADR</span></a> onto a FPGA board. <a href="https://mastodon.social/tags/VHDL" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>VHDL</span></a>, <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Verilog</span></a>, does not matter much. Who is up for a fun challange? <a href="https://mastodon.social/tags/LispMachine" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>LispMachine</span></a></p>
Riley S. Faelan<p>In a better world, <a href="https://toot.cat/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Verilog</span></a> would have <code>/clk</code> instead of <code>posedge clk</code>, <code>\clk</code> instead of <code>negedge clk</code>, and <code>_clk</code> to mean 'clock is down'.</p>
Flux<p>The <a href="https://mastodon.social/tags/Verilog" class="mention hashtag" rel="nofollow noopener noreferrer" target="_blank">#<span>Verilog</span></a> source for all four dev boards and Verilator simulation is available on GitHub under the MIT licence: <a href="https://github.com/projf/projf-explore/tree/main/graphics/fpga-graphics" rel="nofollow noopener noreferrer" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">github.com/projf/projf-explore</span><span class="invisible">/tree/main/graphics/fpga-graphics</span></a></p>
Andrewoften I see RTL designers use non-blocking assignment everywhere, with or without a real need for it, unnecessary complicating the behavior, including resetting logic, utilizing excessive memory, and introducing unnecessary latencies<br>I guess they were once taught about propagation delays and pipelining as a measure of managing them, and since then try to make ad-hoc pipeline out of everything<br>still I find it lame and prefer to make everything combinational if possible, and only introduce extra memory if synthesis fails for given timing constraints<br><br><a class="hashtag" href="https://stereophonic.space/tag/hdl" rel="nofollow noopener noreferrer" target="_blank">#HDL</a> <a class="hashtag" href="https://stereophonic.space/tag/vhdl" rel="nofollow noopener noreferrer" target="_blank">#VHDL</a> <a class="hashtag" href="https://stereophonic.space/tag/systemverilog" rel="nofollow noopener noreferrer" target="_blank">#SystemVerilog</a> <a class="hashtag" href="https://stereophonic.space/tag/verilog" rel="nofollow noopener noreferrer" target="_blank">#Verilog</a>
Andrewfor <a class="hashtag" href="https://stereophonic.space/tag/systemrdl" rel="nofollow noopener noreferrer" target="_blank">#SystemRDL</a> and similar languages there are (synthesisable) register block generators, having <a class="hashtag" href="https://stereophonic.space/tag/axi" rel="nofollow noopener noreferrer" target="_blank">#AXI</a> or AXI Lite on one end and a bunch on signals corresponding to the fields on another<br>similar generated blocks for parsing and forming AXI Stream should be a thing as well, turning an octet stream into a structure together with a validity and no-longer-needed signals, or vice versa<br><br><a class="hashtag" href="https://stereophonic.space/tag/hdl" rel="nofollow noopener noreferrer" target="_blank">#HDL</a> <a class="hashtag" href="https://stereophonic.space/tag/vhdl" rel="nofollow noopener noreferrer" target="_blank">#VHDL</a> <a class="hashtag" href="https://stereophonic.space/tag/systemverilog" rel="nofollow noopener noreferrer" target="_blank">#SystemVerilog</a> <a class="hashtag" href="https://stereophonic.space/tag/verilog" rel="nofollow noopener noreferrer" target="_blank">#Verilog</a> <a class="hashtag" href="https://stereophonic.space/tag/hls" rel="nofollow noopener noreferrer" target="_blank">#HLS</a>
ExploreLive feeds
Mastodon is the best way to keep up with what's happening.
Follow anyone across the fediverse and see it all in chronological order. No algorithms, ads, or clickbait in sight.
Create accountLoginDrag & drop to upload